1. Field of the Invention
This invention relates to a virtual type static semiconductor memory device which employs dynamic memory cells and has the function of refreshing data in the memory cells.
2. Description of the Related Art
Recently a data write/read semiconductor memory device (RAM) has been increased in its capacity. Some semiconductor memory devices can store millions of data on a semiconductor chip as small as 1 mm.sup.2 /2. As a memory cell used as the smallest unit for storing one data, two types are known: a dynamic memory cell necessary to retain stored data and a static memory cell which retains data unless a power supply is interrupted. Six or four transistors and two resistors are necessary to constitute a static memory cell. On the other hand, the dynamic memory cell is constituted by, as shown in FIG. 1, one transistor 51 and one capacitor 52 for storing data as a charge. In FIG. 1, reference numeral 53 shows a word line for selecting a memory cell and 54, a bit line for supplying write data which comes from a selected memory cell. A dynamic RAM employing dynamic memory cells has an advantage in that a large capacity can readily be obtained due to a less number of component elements.
Recently a virtual type static RAM device has been proposed which eliminates the user's cumbersome operation, that is, a controlled refresh operation necessary to hold data in the dynamic RAM. This type of static RAM device can be employed as in the case of an "apparently easy-to-handle" static RAM device.
FIG. 2 is a block diagram showing an arrangement of a conventional virtual type static RAM device. This RAM device comprises address buffer 11 having a normal dynamic RAM, row decoder 12, dynamic memory cells of the type as shown in FIG. 1, sense amplifier 14, column decoder 15, data input/output buffer 16, chip control circuit 17, refresh timer 18, refresh control circuit 19, refresh address counter 20 and address multiplexer 21.
Refresh timer 18 generates a signal of a predetermined cycle. Refresh control circuit 19 enables a refresh control signal RFSH for each given cycle of a signal generated from timer 18 as well as a clock signal CK for performing an up-count or down-count each time a signal FSH is output relative to a row to be enabled. Refresh address counter 20 generates a refresh address by counting up or down the clock signal CK coming from refresh control circuit 19. Address multiplexer 21 selects a refresh address from refresh address counter 20 during the enabling of a refresh control signal RFSH and selects a refresh address to row decoder 12, and selects a normal address from address buffer 11 during the disabling period of the refresh control signal RFSH and supplies the normal address. The refresh control signal RFSH is supplied to sense amplifier 14. Sense amplifier 14 allows data which is read out from memory array 13 during the enabling of the signal RFSH to be amplified and again written into memory array 13.
FIGS. 3 and 4 are timing charts showing an operation of a conventional virtual type static RAM device as set out above.
As appreciated from the timing chart of FIG. 3, a chip enable signal CE as well as an address input external to the RAM is supplied to address buffer 11 during the time period in which the refresh control signal RFSH is not enabled or the internal refresh operation is not performed. By so doing, the RAM allows a read-out operation. In this case, an address received upon the enabling (a low level) of the chip enable signal CE is input from address buffer 11 to column decoder 15 and directly to address multiplexer 21. Since upon the enabling of the chip enable signal CE the refresh control signal RFSH is not enabled (a low level), address multiplexer 21 selects a normal address from address buffer 11 and supplies it to row decoder 12. Row decoder 12 selects a word line for normal access to an address corresponding to an address input. Upon the selection of the word line the data of the memory cell connected to the selected word line is read onto sense amplifier 14 where that data signal is amplified. Of data from the memory cells which are amplified by sense amplifier 14, only that data selected by column decoder 15 is delivered as output data relative to the RAM via data input/output buffer 16.
When a refresh control signal RFSH is enabled (a high level) by refresh control signal RFSH after the completion of the reading of the data from the memory cell, address multiplexer 21 allows a refresh address which is generated at refresh address counter 20 to be delivered to row decoder 12. Row decoder 12 selects an enable word line associated with the refresh address in memory cell array 13. The data which is stored in the memory cell associated with the word line is supplied to sense amplifier 14 for a refreshing operation to be operated. That is, the data signal is amplified by sense amplifier 14 and then the amplified data signal is written again into the original memory cell in array 13. After the completion of the refreshing operation, the refresh control signal RFSH is disabled and chip enable signal CE is again enabled, placing address buffer 11 in readiness for the next normal access input signal. Since the data which is amplified by sense amplifier 14 at the time of the aforementioned refresh operation need not be delivered relative to the RAM, data input/output buffer 16 continues outputting the data during the making of the refresh operation preceding the refresh operation.
As appreciated from the timing chart of FIG. 4, the fresh control signal RFSH is already enabled in the start of a normal access operation by the RAM on the basis of the address input and chip enable signal CE. When the normal access operation is performed with the refresh control signal RFSH already enabled in the operation of the normal access operation and with the refresh operation interrupted in the making of the refresh operation, then the refresh operation is unfinished and hence the data already stored in the memory cell is changed into different data, causing the RAM to operate erroneously. In the case where the refresh control signal RFSH is already enabled upon the making of the normal access operation, the refresh operation is performed to the end. In place of the enable word line, a word line for normal access to the address represented by the address input is selected, after the completion of the refresh operation, and then a normal read operation is carried out. It is to be noted that the enable word line as well as the word line for normal access is selected as the word line, but that these word lines are exactly of the same type.
In the conventional RAM device, if the refresh operation is already performed when a normal access operation is to be performed, the normal access operation has to be delayed until the refresh operation is completed. At this time, the normal access time will be delayed by an extent corresponding to the refresh operation. Let it be assumed that, for example, an access time is 100 nano-seconds when the normal access operation is performed with the refresh operation not done. If, on the other hand, the normal access operation is performed with the refresh operation done, then the access time will be 150 nano-seconds at max. provided that 50 nano-seconds are required for refresh operation. Since the cycle of the refresh timer in general upon using the dynamic memory timer may be about 100 microseconds, the probability of the timing in which the refresh operation is finished upon the normal access operation will be 50 nano-seconds/100 micro-seconds=1/2000. However, the speed of the system using the RAM needs to be set at 150 nano-seconds, a time corresponding to the worst time of the RAM. That is, the aforementioned operation is performed at a rapid speed of 100 nano-seconds at 1999 times out of 2000 times while, on the other hand, it is performed at a slow speed of 150 nano-seconds once out of 2000 times. It is, therefore, necessary to design the system such that all the associated access time be set to 150 nano-seconds.
As appreciated from the above, the conventional virtual type static semiconductor memory device has the disadvantage in that the whole system's speed is determined by the slow access time as set out above in connection with the probability.